1. Field of The Invention
The present invention relates to a chemical vapor deposition process for forming bismuth-containing material films on a substrate for applications such as the manufacture of ferroelectric memory devices.
2. Description of the Related Art
In recent years, ferroelectric materials have been the focus of widespread interest as components of non-volatile memory devices.
Non-volatile ferroelectric memory devices function by storage of information through the polarization of a thin ferroelectric material layer reposed between two plates of a capacitor structure. Each such ferroelectric capacitor is connected to a transistor to form a storage cell, in which the transistor controls the access of the read-out electronics to the capacitor. The transistor therefore is connected to bit-line and word-line elements, to constitute the storage cell.
The ferroelectric material may be utilized in a stacked capacitor structure which overlies the top of the transistor. The transistor drain (e.g., of a MOSFET structure) is connected to the bottom electrode of the capacitor by a plug formed of suitable materials such as polysilicon or tungsten.
Information subsequently can be changed in the ferroelectric memory cell by applying an electric field to the thin ferroelectric material layer to reverse ("flip") the polarization characteristic of the ferroelectric material. Ferroelectric memories (FRAMs), in contrast to dynamic random access memories (DRAMs), have the advantages of retaining stored information in the event of termination of the power supply, and do not require refresh cycles.
In such memory applications, ferroelectric materials desirably have the following electrical properties: (1) a low coercive field characteristic, facilitating use of a low voltage power supply; (2) a high remnant polarization characteristic, ensuring highly reliable information storage; (3) absence of significant fatigue or life-time deterioration characteristics; (4) absence of any imprint which would alter the stored information (e.g., leading to a preference of a certain polarization such as a logical "1" over a logical "0" character) or otherwise impair the ability to "read" the stored information; and (5) extended retention time, for reliable data storage over an extended period of time.
The foregoing electrical property criteria are satisfied in the layered pseudo-perovskite or "Aurivillius" phase of materials such as strontium bismuth tantalate, SrBi.sub.2 Ta.sub.2 O.sub.9. This strontium bismuth tantalate composition is sometimes hereinafter referred to as "SBT." As a result of these favorable characteristics, significant efforts have been initiated to integrate SBT in memory devices. Ferroelectric capacitor structures utilizing SBT as the ferroelectric material have been made in the prior art by sol-gel techniques and demonstrate superior electrical properties.
Unfortunately, however, such sol-gel methodology permits only a low integration density to be achieved. Some improvement in the sol-gel methodology may be gained by mist or electrospray methods, permitting fabrication of memories up to 4 megabit in capacity.
To achieve higher integration density of SBT with smaller structure sizes (e.g., having a minimal feature size below about 0.7 micron), it is necessary to utilize chemical vapor deposition (CVD) processes, since CVD affords better conformality and step coverage than layers produced by any other deposition method. Further, the CVD process yields deposited films having a high film uniformity, high film density, and the capability to grow very thin films at high throughput and low cost.
Concerning relevant art to the present invention, U.S. Pat. No. 5,527,567 to Desu et al. discloses CVD of a ferroelectric layered structure in a single-step or a two-step process at temperatures which in the single-step process may be in the range of 450-600.degree. C., and in the two-step process may be in the range of 550-700.degree. C. in the first step and 600-700.degree. C. in the second step. The Desu et al. patent describes post-deposition treatment steps including annealing, deposition of a top electrode, and further annealing.
Desu et al. describe as suitable precursors for the respective bismuth, strontium and tantalum components of the SBT film triphenyl bismuth, strontium bis(2,2,6,6-tetramethylheptane-2,5-dionate)tetraglyme adduct and tantalum pentaethoxide, with such precursors being utilized in a solvent medium such as an 8:2:1 mixture of tetrahydrofuran, isopropanol and tetraglyme. The Desu et al patent mentions Bi(thd).sub.3.
The Desu et al patent describes vaporization at temperatures of 60-300.degree. C. In a specific embodiment, Desu et al. teach evaporation of the precursors in a vaporizer by direct liquid injection, at a temperature in the range of 250-320.degree. C., followed by growth of films from the vaporized precursor at a temperature in the range of 450-800.degree. C. on a Pt/Ti/SiO.sub.2 /Si or sapphire substrate, with post-deposition annealing at 750.degree. C.
A related patent of Desu et al. is U.S. Pat. No. 5,478,610.
U.S. Pat. No. 5,648,114 describes a method of fabricating an electronic device including CVD deposition of a layered superlattice material which is post-treated to improve its properties.
The art continues to seek improvement in SBT and ferroelectric memory technologies.
It is an object of the present invention to provide an improved CVD process for the deposition of bismuth oxide materials (e.g., SrBi.sub.2 Ta.sub.2 O.sub.9, Bi.sub.4 Ti.sub.3 O.sub.12, etc.), including materials of such type for formation of ferroelectric thin films for applications such as ferroelectric memory devices.
Other objects of the invention will be more fully apparent from the ensuing disclosure and appended claims.